As a variable divider of this type, a variable divider having two types of frequency division numbers for an input clock signal and capable of switching the frequency division numbers in accordance with an external control signal is conventionally used.
[Prior Art 1]
FIG. 13 shows an outline of a conventional variable divider disclosed in non-patent reference 1. A variable divider 100 includes a clock input terminal 101, clock output terminal 102, and control signal input terminal 103, divides an input clock signal from the clock input terminal 101 by a frequency division number determined in accordance with a control signal M input from the control signal input terminal 103, and outputs the frequency-divided clock signal as an output clock signal from the clock output terminal 102.
In this prior art, the variable divider 100 is made up of blocks 100A and 100B. The block 100A includes D-flip-flops (DFFS) 104 to 106 and NOR circuits (NORS) 107 and 108, and the block 100B includes T-flip-flops (TFFs) 109 to 111 and OR circuits (ORs) 112 to 114. Note that the functions of the TFFs and DFFs are described in non-patent reference 2, so an explanation thereof will be omitted.
In the block 100A, an input clock signal from the clock input terminal 101 is applied to the clock terminals (ck) of the DFFs 104 to 106. A ¼ or ⅕ divided signal is obtained at a point P1 by the operations of the DFFs 104 to 106 having received this input clock signal, and the ¼ or ⅕ divided signal is further divided by the TFFs 109 to 111 in the block 100B.
The OR 112 ORs the outputs from the TFFs 109 and 110, the OR 113 ORs the output from the TFF 111 and the control signal M from the control signal terminal 103, the OR 114 ORs the outputs from the ORs 112 and 113, and the output from the OR 114 is applied to the NOR 108 of the block 100A. When the control signal M is level “0”, therefore, the block 100A performs division by 5 only once during division by 32 and performs division by 4 in the rest of the operation, thereby realizing division by 33. When the control signal M is level “1”, the block A performs division by 4 during the whole of division by 32, thereby realizing division by 32.
[Prior Art 2]
FIG. 14 shows an outline of a conventional variable divider disclosed in patent reference 1. A variable divider 200 includes a clock input terminal 201, clock output terminal 202, and control signal input terminal 203, divides a clock signal input from the clock input terminal 201 by a frequency division number determined in accordance with a control signal (external control signal) M input from the control signal input terminal 203, and outputs the frequency-divided clock signal as an output clock signal from the clock output terminal 202. In this prior art, the variable divider 200 includes a divider (½ divider) 204 for low-speed clock, inverting/noninverting unit 205, fixed divider (½ divider) 206, connection device 207, and feedback divider (½ divider) 208, and the inverting/noninverting unit 205 and fixed divider 206 form a signal processor 210. The inverting/noninverting unit 205 has an input terminal 210a and control terminal 210b, the input terminal (the input terminal of the signal processor 210) 210a is connected to the clock input terminal 201 via the divider 204 for low-speed clock, and a feedback path 209 is formed between the control terminal (the control terminal of the signal processor 210) 210b and an output (the output terminal of the signal processor 210) 210c of the fixed divider 206. The connection device 207 and feedback divider 208 are arranged on the feedback path 209. FIG. 15 shows a truth table of the inverting/noninverting unit 205.
[When Feedback Path Is Disconnected]
When the control signal M is level “0”, the connection device 207 turns off the feedback path 209 to disconnect the output 210c of the fixed divider 206 from the control terminal 210b of the inverting/noninverting unit 205. In this case, the level of the control terminal 210b of the inverting/noninverting unit 205 changes to “0”, and, in accordance with the truth table shown in FIG. 15, the inverting/noninverting unit 205 passes the input clock signal without inverting it, and applies the signal as a clock signal before division to the fixed divider 206.
FIG. 16 shows a timing chart when the feedback path 209 is disconnected. FIG. 16(a) denotes a clock signal (master clock) applied to the clock input terminal 201; FIG. 16(b), an input clock signal applied to the input terminal 210a of the inverting/noninverting unit 205; FIG. 16(c), a clock signal before division (a clock signal before division applied to the fixed divider 206) output from the inverting/noninverting unit 205; FIG. 16(d), an output clock signal from the fixed divider 206; and FIG. 16(e), the signal level of the control terminal 210b of the inverting/noninverting unit 205.
In this prior art, the clock signal from the clock input terminal 201 is divided by 2 by the divider 204 for low-speed clock, and the low-speed clock signal is applied as an input clock signal to the input terminal 210a of the inverting/noninverting unit 205. As is apparent from this timing chart, when the control signal M is level “0”, the variable divider 200 generates an output clock signal having one pulse whenever two clock pulses of the input clock signal are applied to the input terminal 210a of the inverting/noninverting unit 205, i.e., whenever four master clocks are applied to the clock input terminal 201, thereby operating as a ¼ divider.
[When Feedback Path Is Connected]
When the control signal M is level “1”, the connection device 207 turns on the feedback path 209 to connect the output 210c of the fixed divider 206 to the control terminal 210b of the inverting/noninverting unit 205. FIG. 17 shows a timing chart when the feedback path 209 is connected. Note that in this timing chart, a delay time Td during which a signal applied to the input terminal 210a of the inverting/noninverting unit 205 is returned to the control terminal 210b of the inverting/noninverting unit 205 through the inverting/noninverting unit 205, fixed divider 206, and feedback path 209 is made slightly larger than a pulse width Tck of the input clock signal.
When the input clock signal rises at a point t1 shown in FIG. 17(b), the inverting/noninverting unit 205 passes the leading edge of this input clock signal without inverting it. Consequently, a clock signal before division rises (the point t1 shown in FIG. 17(c)), and is applied to the fixed divider 206. The fixed divider 206 receives the leading edge (change point) of this clock signal before division, and raises an output clock signal (the point t1 shown in FIG. 17(d)).
The leading edge of this output clock signal is returned to the control terminal 210b of the inverting/noninverting unit 205 via the feedback path 209. That is, the leading edge of the output signal from the fixed divider 206 is applied to the feedback divider 208, and the feedback divider 208 receives the leading edge of the output signal from the fixed divider 206, and raises a feedback signal to be applied to the control signal 210b of the inverting/noninverting unit 205. To the control terminal 210b of the inverting/noninverting unit 205, the leading edge of the feedback signal is input (a point t3 shown in FIG. 17(e)) as it lags behind the leading edge (the leading edge of the first clock pulse: the point t1 in FIG. 17(b)) of the input clock signal applied to the input terminal 210a of the inverting/noninverting unit 205, by the delay time Td, i.e., by a delay time larger than the pulse width Tck of the input clock signal.
While the feedback signal to the control terminal 210b is high, the inverting/noninverting unit 205 inverts the input clock signal from the input terminal 210a. In this case, when the feedback signal to the control terminal 210b of the inverting/noninverting unit 205 rises (the point t3 shown in FIG. 17(e)), the input clock signal to the input terminal 210a of the inverting/noninverting unit 205 has already fallen. Therefore, the inverting/noninverting unit 205 inverts the input clock signal from the input terminal 210a, and raises a clock signal before division (the point t3 shown in FIG. 17(c)). After that, the clock signal before division is a signal obtained by inverting the input clock signal from the input terminal 210a. 
Consequently, between the point t3 and a point t4 shown in FIG. 17(c), a clock pulse (small pulse) PS1 having a pulse width smaller than the pulse width Tck (normal pulse width) of the input clock signal is generated. After that, a clock pulse having the normal pulse width is generated between points t5 and t6. The fixed divider 206 receives the leading edge of the small pulse PS1 of the clock signal before division from the inverting/noninverting unit 205, and lowers an output clock signal (the point t3 shown in FIG. 17(d)). When the clock pulse having the normal pulse width is generated (the point t5 shown in FIG. 17(c)) after the small pulse PS1 is generated, the fixed divider 206 receives the leading edge of this clock pulse, and raises an output clock signal (the point t5 shown in FIG. 17(d)).
The leading edge of this output clock signal is applied to the feedback divider 208, and the feedback signal to the control terminal 210b of the inverting/noninverting unit 205 falls. To the control terminal 210b of the inverting/noninverting unit 205, the trailing edge of the feedback signal is input (a point t7 shown in FIG. 17(e)) as it lags behind the trailing edge (the trailing edge of the second clock pulse: the point t5 shown in FIG. 17(b)) of the input clock signal applied to the input signal 210a of the inverting/noninverting unit 205, by the delay time Td, i.e., by a delay time larger than the pulse width Tck of the input clock signal.
While the feedback signal to the control terminal 210b is low, the inverting/noninverting unit 205 passes the input clock signal from the input terminal 210a without inverting it. In this case, when the feedback signal to the control terminal 210b of the inverting/noninverting unit 205 falls (the point t7 shown in FIG. 17(e)), the input clock signal to the input terminal 210a of the inverting/noninverting unit 205 has already risen. Therefore, the inverting/noninverting unit 205 passes the input clock signal from the input terminal 210a without inverting it, and raises a clock signal before division (the point t7 shown in FIG. 17(c)). After that, the clock signal before division is a signal obtained by passing the input clock signal from the input terminal 210a without inverting it.
Consequently, a small pulse PS2 is generated between the point t7 and a point t8 shown in FIG. 17(c), and a clock pulse having the normal pulse width is generated between points t9 and t10 after that. The fixed divider 206 receives the leading edge of the small pulse PS2 from the inverting/noninverting unit 205, and lowers an output clock signal (the point t7 shown in FIG. 17(d)). After that, the fixed divider 206 receives the leading edge of the clock pulse having the normal pulse width from the inverting/noninverting unit 205, and raises an output clock signal (the point t9 shown in FIG. 17(d)).
By repeating the same operation after that, the variable divider 200 generates an output clock signal having two pulses, if the control signal M is at level “1”, whenever three clock pulses of the input clock signal are applied to the input terminal 210a of the inverting/noninverting unit 205, i.e., whenever six master clocks are applied to the clock input terminal 201, thereby operating as a ⅓ divider.
Patent reference 1: U.S. Pat. No. 5,969,548
Non-patent reference: “CMOS Analog Circuit Design Techniques”, supervised by Boku Iwata, Triceps, Jan. 13, 1998, pp. 236 and 237, FIGS. 16 and 17.
Non-patent reference 2: “HANDBOOK OF LOGIC CIRCUITS”, J. D. LENK, pp. 123–125, Reston Publishing Company, Inc., 1972.
Disclosure of Invention
Problems to be Solved by the Invention
[Problem of Prior Art 1]
The variable divider 100 of prior art 1 has a large number of branch points, so paths C, for example, indicated by the dotted lines in FIG. 13, form critical paths (paths having a large capacitive load and requiring a large driving current), and this makes low power consumption difficult to achieve.
[Problem of Prior Art 2]
The variable divider 200 of prior art 2 has a small number of branch points and does not generate any path having a large capacitive load such as a critical path, so low power consumption can be realized. However, frequency division is performed using both the rise and trailing edges of an input clock signal which is the output of the divider 204 for low-speed clock. If the duty ratio of the input clock signal is not 50%, therefore, jitter Tj (FIG. 18) occurs in the output clock signal, and this deteriorates the noise performance.
[Reason for Jitter Occurrence]
The variable divider 200 of prior art 2 forms a low-speed input clock signal by dividing a high-frequency clock signal (master clock) by 2 by the divider 204 for low-speed clock. In this case, an input clock signal is raised by receiving the first leading edge of the master clock, and lowered by receiving the second leading edge.
In the divider 204 for low-speed clock, it is difficult to make the operation time before the input clock signal is raised by receiving the leading edge of the master clock equal to the operation time before the input clock signal is lowered. By this difference between the operation times of rise/fall, the duty ratio of the input clock signal becomes higher or lower than 50% as an ideal value. It is generally very difficult to accurately set the duty ratio of a high-frequency signal at 50/50, and even a ratio of about 40/60 is evaluated as relatively good.
FIG. 18 shows a case in which the duty ratio (ON duty) of an input clock signal is 50% or more. In this case, the first clock pulse of an output clock signal is generated in synchronism with the leading edge (a point t1 in FIG. 18(a)), but the second clock pulse is not generated in synchronism with the leading edge (a point t5 in FIG. 18(a)) of the clock signal, so the jitter Tj occurs. The jitter Tj similarly occurs when the duty ratio (ON duty) of the input clock signal is 50% or less.
The present invention has been made to solve the above problems, and has as its object to provide a variable division method and variable divider which can realize low power consumption, and can also prevent deterioration of the noise performance by substantially eliminating jitter occurring in an output clock signal.
Means for Solving the Problems
To achieve the above object, the present invention has a signal processor which forms a clock signal before division by inverting/without inverting an input clock signal applied to an input terminal in accordance with a level of a signal applied to a control terminal, divides the clock signal before division by a predetermined frequency division number on the basis of a change point, which corresponds to a change point in one direction of the input clock signal, in a clock pulse having a pulse width larger than a predetermined pulse width in the clock signal before division, and outputs the frequency-divided signal as an output clock signal from an output terminal, and a connection device which connects/disconnects, in accordance with an external control signal, a feedback path which is formed between the output terminal and control terminal of the signal processor and functions as a path of a signal to be returned to the control terminal, wherein a delay time during which a signal applied to the input terminal of the signal processor is returned to the control terminal through the feedback path is made larger than a pulse width of the input clock signal.
In the present invention, the feedback path formed between the output terminal and control terminal of the signal processor is connected or disconnected in accordance with an external control signal. Note that in the following description, the initial inverted/noninverted state in the signal processor is set to the noninverting state, and the frequency division number is 2, for the sake of convenience of explanation.
[When Feedback Path Is Disconnected]
When the feedback path is disconnected, the signal processor forms a clock signal before division directly from an input clock signal without inverting it, and obtains an output clock signal by dividing this clock signal before division by 2. In this way, the variable divider of the present invention operates as a ½ divider.
[When Feedback Path Is Connected]
When the feedback path is connected, the signal processor initially forms a clock signal before division directly from an input clock signal without inverting it. The signal processor receives the first leading edge (a change point corresponding to the leading edge of the input clock signal) of this clock signal before division, and raises an output clock signal. The leading edge of this output clock signal is returned to the control terminal via the feedback path.
To the control terminal of the signal processor, the leading edge of the output clock signal is returned as it lags behind the leading edge (the leading edge of the first clock pulse) of the input clock signal applied to the input terminal of the signal processor, by the pulse width of the input clock signal. While the signal (feedback signal) returned to the control terminal is high, the signal processor inverts the input clock signal. Consequently, a clock pulse (small pulse) smaller than the pulse width (normal pulse width) of the input clock pulse is generated in the clock signal before division, and a clock pulse having the normal pulse width is generated after that.
If it is determined that a clock pulse larger than a predetermined pulse width is larger than the pulse width of the small pulse, the signal processor invalidates the small pulse of the clock signal before division, validates the clock pulse having the normal pulse width which is generated after that, receives the leading edge of this clock pulse having the normal pulse width, and lowers an output clock signal. The trailing edge of this output signal is returned to the control terminal of the signal processor via the feedback path.
To the control terminal of the signal processor, the trailing edge of the output clock signal is returned as it lags behind the trailing edge (the trailing edge of the second clock pulse) of the input clock signal applied to the input terminal of the signal processor, by a delay time larger than the pulse width of the input clock signal. While the signal (feedback signal) returned to the control terminal is low, the signal processor forms a clock signal before division directly from the input clock signal without inverting it. Consequently, a clock pulse (small pulse) smaller than the pulse width (normal pulse width) of the input clock signal is generated in the clock signal before division, and a clock pulse having the normal pulse width is generated after that.
In the same manner as above, the signal processor invalidates the small pulse of the clock signal before division, validates the clock pulse having the normal pulse width which is generated after that, receives the leading edge (a change point corresponding to the leading edge of the input clock signal) of this clock pulse having the normal pulse width, and raises an output clock signal. In this manner, the variable divider of the present invention operates as a ⅓ divider. During this dividing operation, the signal processor forms an output clock signal by receiving the leading edge of the clock pulse having the normal pulse width, i.e., a change point corresponding to the leading edge of the input clock signal (a change point corresponding to a change point in one direction of the input clock signal). Therefore, no jitter occurs even if the duty ratio of the input clock signal is higher or lower than 50% as an ideal value.
Note that in the present invention, the signal processor can be formed by an inverting/noninverting unit and fixed divider. In this case, the fixed divider can be given a function “which extracts, from the clock signal before division from the inverting/noninverting unit, only a clock pulse larger than a predetermined pulse width as a valid clock signal”, or the inverting/noninverting unit can be given a function “which outputs only a clock pulse larger than a predetermined pulse width as a clock signal before division”.
Also, in the present invention, the delay time (the time during which the signal applied to the input terminal of the signal processor is returned to the control terminal through the feedback path) is made larger than the pulse width of the input clock pulse.
However, this delay time may be naturally produced as the total of delay times produced in the route through which the signal applied to the input terminal is returned to the output terminal through the feedback path, or may also be ensured by intentionally forming a delay circuit or the like in this route.